Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Two common types of flash memory array architectures are the “NOR” and “NAND” architectures. The architecture names refer to the resemblance that the memory cell configuration of each architecture has to a basic NOR or NAND gate circuit, respectively.
In the NOR array architecture, the floating gate memory cells of the memory array are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to word select lines (wordlines) and their drains are connected to column bitlines. The source of each floating gate memory cell is typically connected to a common source line.
A NAND array architecture also arranges its array of floating gate memory cells in a matrix such that the gates of each floating gate memory cell of the array are connected by rows to wordlines. Each memory cell, however, is not directly connected to a source line and a column bit line. The memory cells of the array are instead arranged together in strings. Each string typically comprises 8, 16, 32, or more cells. The memory cells in the string are connected together in series, source to drain, between a common sourceline and a column bitline.
As the performance of electronic systems increase, the performance of flash memory devices in the systems should increase as well. A performance increase can include improving both the speed and the memory density of the devices. One way to accomplish both of these criteria is to reduce the memory device size.
One problem with decreasing the size of a NAND flash memory device is the floating gate-to-floating gate coupling that occurs as the memory cells get closer together. The overall height of the floating gates are not reduced much since that also reduces the coupling of the wordline and impacts the program and erase operations on the cells. The increased capacitive coupling between the floating gates creates a data pattern sensitivity such that data programmed on one cell can affect the verification and reading of an adjacent cell.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce the effect of capacitive coupling between adjacent floating gates.